summaryrefslogtreecommitdiff
path: root/arch/sh/syscall_arch.h
blob: 628d8d3741226183b20cd2b3f5f0569a36969751 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
#define __SYSCALL_LL_E(x) \
((union { long long ll; long l[2]; }){ .ll = x }).l[0], \
((union { long long ll; long l[2]; }){ .ll = x }).l[1]
#define __SYSCALL_LL_O(x) __SYSCALL_LL_E((x))
#define __SYSCALL_LL_PRW(x) 0, __SYSCALL_LL_E((x))

/* The extra OR instructions are to work around a hardware bug:
 * http://documentation.renesas.com/doc/products/mpumcu/tu/tnsh7456ae.pdf
 */
#define __asm_syscall(trapno, ...) do {   \
	__asm__ __volatile__ (                \
		"trapa #31\n"            \
		"or r0, r0\n"                     \
		"or r0, r0\n"                     \
		"or r0, r0\n"                     \
		"or r0, r0\n"                     \
		"or r0, r0\n"                     \
	: "=r"(r0) : __VA_ARGS__ : "memory"); \
	return r0;                            \
	} while (0)

static inline long __syscall0(long n)
{
	register long r3 __asm__("r3") = n;
	register long r0 __asm__("r0");
	__asm_syscall(16, "r"(r3));
}

static inline long __syscall1(long n, long a)
{
	register long r3 __asm__("r3") = n;
	register long r4 __asm__("r4") = a;
	register long r0 __asm__("r0");
	__asm_syscall(17, "r"(r3), "r"(r4));
}

static inline long __syscall2(long n, long a, long b)
{
	register long r3 __asm__("r3") = n;
	register long r4 __asm__("r4") = a;
	register long r5 __asm__("r5") = b;
	register long r0 __asm__("r0");
	__asm_syscall(18, "r"(r3), "r"(r4), "r"(r5));
}

static inline long __syscall3(long n, long a, long b, long c)
{
	register long r3 __asm__("r3") = n;
	register long r4 __asm__("r4") = a;
	register long r5 __asm__("r5") = b;
	register long r6 __asm__("r6") = c;
	register long r0 __asm__("r0");
	__asm_syscall(19, "r"(r3), "r"(r4), "r"(r5), "r"(r6));
}

static inline long __syscall4(long n, long a, long b, long c, long d)
{
	register long r3 __asm__("r3") = n;
	register long r4 __asm__("r4") = a;
	register long r5 __asm__("r5") = b;
	register long r6 __asm__("r6") = c;
	register long r7 __asm__("r7") = d;
	register long r0 __asm__("r0");
	__asm_syscall(20, "r"(r3), "r"(r4), "r"(r5), "r"(r6), "r"(r7));
}

static inline long __syscall5(long n, long a, long b, long c, long d, long e)
{
	register long r3 __asm__("r3") = n;
	register long r4 __asm__("r4") = a;
	register long r5 __asm__("r5") = b;
	register long r6 __asm__("r6") = c;
	register long r7 __asm__("r7") = d;
	register long r0 __asm__("r0") = e;
	__asm_syscall(21, "r"(r3), "r"(r4), "r"(r5), "r"(r6), "r"(r7), "0"(r0));
}

static inline long __syscall6(long n, long a, long b, long c, long d, long e, long f)
{
	register long r3 __asm__("r3") = n;
	register long r4 __asm__("r4") = a;
	register long r5 __asm__("r5") = b;
	register long r6 __asm__("r6") = c;
	register long r7 __asm__("r7") = d;
	register long r0 __asm__("r0") = e;
	register long r1 __asm__("r1") = f;
	__asm_syscall(22, "r"(r3), "r"(r4), "r"(r5), "r"(r6), "r"(r7), "0"(r0), "r"(r1));
}

#define SYSCALL_IPC_BROKEN_MODE

#define SIOCGSTAMP_OLD   (2U<<30 | 's'<<8 | 100 | 8<<16)
#define SIOCGSTAMPNS_OLD (2U<<30 | 's'<<8 | 101 | 8<<16)