summaryrefslogtreecommitdiff
path: root/src/setjmp
AgeCommit message (Collapse)AuthorLines
2019-09-26fix mips setjmp/longjmp fpu state on r6, related issuesRich Felker-24/+12
mips32 has two fpu register file variants: FR=0 with 32 32-bit registers, where pairs of neighboring even/odd registers are used to represent doubles, and FR=1 with 32 64-bit registers, each of which can store a single or double. up through r5 (our "mips" arch), the supported ABI uses FR=0, but modern compilers generate "fpxx" model code that can safely operate with either model. r6, which is an incompatible but similar ISA, drops FR=0 and only provides the FR=1 model. as such, setjmp and longjmp, which depended on being able to save and restore call-saved doubles by storing and loading their 32-bit halves, were completely broken in the presence of floating point code on mips r6. to fix this, use the s.d and l.d mnemonics to store and load fpu registers. these expand to the existing swc1 and lwc1 instructions for pairs of 32-bit fpu registers on mips1, but on mips2 and later they translate directly to the 64-bit sdc1 and ldc1. with FR=0, sdc1 and ldc1 behave just like the pairs of swc1 and lwc1 instructions they replace, storing or loading the even/odd pair of fpu registers that can be treated as separate single-precision floats or as a unit representing a double. but with FR=1, they store/load individual 64-bit registers. this yields the ABI-correct behavior on mips r6, and should make linking of pre-r6 (plain "mips") code with "fp64" model code workable, although this is and will likely remain unsupported usage. in addition to the mips r6 problem this change fixes, reportedly clang's internal assembler refuses to assemble swc1 and lwc1 instructions for odd register indices when building for "fpxx" model (the default). this caused setjmp and longjmp not to build. by using the s.d and l.d forms, this problem is avoided too. as a bonus, code size is reduced everywhere but mips1.
2019-09-26arm: fix setjmp and longjmp asm for armv8-aSzabolcs Nagy-0/+14
armv8 removed the coprocessor instructions other than cp14, so on an armv8 system the related hwcaps should never be set. new llvm complains about the use of coprocessor instructions in armv8-a mode (even though they are never executed at runtime), so ifdef them out when musl is built for armv8.
2019-06-14add riscv64 architecture supportRich Felker-0/+83
Author: Alex Suykov <alex.suykov@gmail.com> Author: Aric Belsito <lluixhi@gmail.com> Author: Drew DeVault <sir@cmpwn.com> Author: Michael Clark <mjc@sifive.com> Author: Michael Forney <mforney@mforney.org> Author: Stefan O'Rear <sorear2@gmail.com> This port has involved the work of many people over several years. I have tried to ensure that everyone with substantial contributions has been credited above; if any omissions are found they will be noted later in an update to the authors/contributors list in the COPYRIGHT file. The version committed here comes from the riscv/riscv-musl repo's commit 3fe7e2c75df78eef42dcdc352a55757729f451e2, with minor changes by me for issues found during final review: - a_ll/a_sc atomics are removed (according to the ISA spec, lr/sc are not safe to use in separate inline asm fragments) - a_cas[_p] is fixed to be a memory barrier - the call from the _start assembly into the C part of crt1/ldso is changed to allow for the possibility that the linker does not place them nearby each other. - DTP_OFFSET is defined correctly so that local-dynamic TLS works - reloc.h LDSO_ARCH logic is simplified and made explicit. - unused, non-functional crti/n asm files are removed. - an empty .sdata section is added to crt1 so that the __global_pointer reference is resolvable. - indentation style errors in some asm files are fixed.
2018-06-19add m68k portRich Felker-0/+32
three ABIs are supported: the default with 68881 80-bit fpu format and results returned in floating point registers, softfloat-only with the same format, and coldfire fpu with IEEE single/double only. only the first is tested at all, and only under qemu which has fpu emulation bugs. basic functionality smoke tests have been performed for the most common arch-specific breakage via libc-test and qemu user-level emulation. some sysvipc failures remain, but are shared with other big endian archs and will be fixed separately.
2017-10-13fix access by setjmp and longjmp to __hwcap on arm built as thumb2Rich Felker-0/+2
this is a subtle issue with how the assembler/linker work. for the adr pseudo-instruction used to find __hwcap, the assembler in thumb mode generates a 16-bit thumb add instruction which can only represent word-aligned addresses, despite not knowing the alignment of the label. if the setjmp function is assigned a non-multiple-of-4 address at link time, the load then loads from the wrong address (the last instruction rather than the data containing the offset) and ends up reading nonsense instead of the value of __hwcap. this in turn causes the checks for floating-point/vector register sets (e.g. IWMMX) to evaluate incorrectly, crashing when setjmp/longjmp try to save/restore those registers. fix based on bug report by Felix H├Ądicke.
2017-08-11ppc64: fix setjmp/longjmp handling of TOC pointerBobby Bingham-10/+25
The TOC pointer is constant within a single dso, but needs to be saved and restored around cross-dso calls. The PLT stub saves it to the caller's stack frame, and the linker adds code to the caller to restore it. With a local call, as within a single dso or with static linking, this doesn't happen and the TOC pointer is always in r2. Therefore, setjmp/longjmp need to save/restore the TOC pointer from/to different locations depending on whether the call to setjmp was a local or non-local call. It is always safe for longjmp to restore to both r2 and the caller's stack. If the call to setjmp was local, and only r2 matters and the stack location will be ignored, but is required by the ABI to be reserved for the TOC pointer. If the call was non-local, then only the stack location matters, and whatever is restored into r2 will be clobbered anyway when the caller reloads r2 from the stack. A little extra care is required for sigsetjmp, because it uses setjmp internally. After the second return from this setjmp call, r2 will contain the caller's TOC pointer instead of libc's TOC pointer. We need to save and restore the correct libc pointer before we can tail call to __sigsetjmp_tail.
2016-12-17make arm setjmp/longjmp asm thumb2-compatibleRich Felker-2/+6
sp cannot be used in the ldm/stm register set in thumb mode.
2016-11-11add s390x portBobby Bingham-0/+48
2016-05-08add powerpc64 portBobby Bingham-0/+155
2016-04-18add mips n32 port (ILP32 ABI for mips64)Rich Felker-0/+70
based on patch submitted by Jaydeep Patil, with minor changes.
2016-03-06add powerpc soft-float supportFelix Fietkau-16/+22
Some PowerPC CPUs (e.g. Freescale MPC85xx) have a completely different instruction set for floating point operations (SPE). Executing regular PowerPC floating point instructions results in "Illegal instruction" errors. Make it possible to run these devices in soft-float mode.
2016-03-06add mips64 portRich Felker-0/+71
patch by Mahesh Bodapati and Jaydeep Patil of Imagination Technologies.
2016-01-20switch sh and mips setjmp asm from .sub system to .S filesRich Felker-109/+12
2015-11-11use correct nofpu versions of setjmp/longjmp used on sh-nofpu-fdpicRich Felker-0/+4
when adding the fdpic subarchs, the need for these sub files was overlooked. thus setjmp and longjmp performed illegal instructions.
2015-11-10explicitly assemble all arm asm sources as UALRich Felker-0/+2
these files are all accepted as legacy arm syntax when producing arm code, but legacy syntax cannot be used for producing thumb2 with access to the full ISA. even after switching to UAL, some asm source files contain instructions which are not valid in thumb mode, so these will need to be addressed separately.
2015-11-09remove non-working pre-armv4t support from arm asmRich Felker-6/+2
the idea of the three-instruction sequence being removed was to be able to return to thumb code when used on armv4t+ from a thumb caller, but also to be able to run on armv4 without the bx instruction available (in which case the low bit of lr would always be 0). however, without compiler support for generating such a sequence from C code, which does not exist and which there is unlikely to be interest in implementing, there is little point in having it in the asm, and it would likely be easier to add pre-armv4t support via enhanced linker handling of R_ARM_V4BX than at the compiler level. removing this code simplifies adding support for building libc in thumb2-only form (for cortex-m).
2015-11-09use vfp mnemonics rather than hard-coded opcodes in arm setjmp/longjmpRich Felker-2/+10
the code to save/restore vfp registers needs to build even when the configured target does not have fpu; this is because code using vfp fpu (but with the standard soft-float EABI) may call a libc built for a soft-float only, and the EABI considers these registers call-saved when they exist. thus, extra directives are used to force the assembler to allow vfp instructions and to avoid marking the resulting object files as requiring vfp. moving away from using hard-coded opcode words is necessary in order to eventually support producing thumb2-only output for cortex-m. conditional execution of these instructions based on hwcap flags was already implemented. when building for arm (non-thumb) output, the only currently-supported configuration, this commit does not change the code emitted.
2015-04-24fix build regression in sh-nofpu subarch due to missing symbolRich Felker-0/+3
commit 646cb9a4a04e5ed78e2dd928bf9dc6e79202f609 switched sigsetjmp to use the new hidden ___setjmp symbol for setjmp, but the nofpu variant of setjmp.s was not updated to match.
2015-04-19remove invalid PLT calls from or1k asmRich Felker-0/+3
analogous to commit 646cb9a4a04e5ed78e2dd928bf9dc6e79202f609 for sh.
2015-04-19remove possible-textrels from powerpc asmRich Felker-0/+3
these are perfectly fine with ld-time symbol binding, but otherwise result in textrels. they cannot be replaced with @PLT jump targets because the PLT thunks require a GOT register to be setup, so use a hidden alias instead.
2015-04-19remove invalid PLT calls from microblaze asmRich Felker-0/+3
analogous to commit 646cb9a4a04e5ed78e2dd928bf9dc6e79202f609 for sh.
2015-04-19remove invalid PLT calls from sh asmRich Felker-0/+3
these are perfectly fine with ld-time symbol binding, but if the calls go through a PLT thunk, they are invalid because the caller does not setup a GOT register. use a hidden alias to bypass the issue.
2015-04-18remove the last of possible-textrels from i386 asmRich Felker-0/+3
none of these are actual textrels because of ld-time binding performed by -Bsymbolic-functions, but I'm changing them with the goal of making ld-time binding purely an optimization rather than relying on it for semantic purposes. in the case of memmove's call to memcpy, making it explicit that the memmove asm is assuming the forward-copying behavior of the memcpy asm is desirable anyway; in case memcpy is ever changed, the semantic mismatch would be apparent while editing memmcpy.s.
2015-03-11add aarch64 portSzabolcs Nagy-0/+48
This adds complete aarch64 target support including bigendian subarch. Some of the long double math functions are known to be broken otherwise interfaces should be fully functional, but at this point consider this port experimental. Initial work on this port was done by Sireesh Tripurari and Kevin Bortis.
2015-01-30fix missing comma in sh setjmp asmTrutz Behn-1/+1
this typo did not result in an erroneous setjmp with at least binutils 2.22 but fix it for clarity and compatibility with potentially stricter sh assemblers.
2014-11-23fix build regression in arm asm for setjmp/longjmp with old assemblersRich Felker-2/+2
2014-11-23arm assembly changes for clang compatibilityJoakim Sindholt-2/+2
2014-07-18add or1k (OpenRISC 1000) architecture portStefan Kristiansson-0/+49
With the exception of a fenv implementation, the port is fully featured. The port has been tested in or1ksim, the golden reference functional simulator for OpenRISC 1000. It passes all libc-test tests (except the math tests that requires a fenv implementation). The port assumes an or1k implementation that has support for atomic instructions (l.lwa/l.swa). Although it passes all the libc-test tests, the port is still in an experimental state, and has yet experienced very little 'real-world' use.
2014-07-08fix typo in microblaze setjmp asmRich Felker-1/+1
r24 was wrongly being saved at a misaligned offset of 30 rather than the correct offset of 40 in the jmp_buf. the exact effects of this error have not been studied, but it's clear that the value of r24 was lost across setjmp/longjmp and the saved values of r21 and/or r22 may also have been corrupted.
2014-02-27add nofpu subarchs to the sh arch, and properly detect compiler's fpu configRich Felker-0/+47
2014-02-27rename superh port to "sh" for consistencyRich Felker-0/+0
linux, gcc, etc. all use "sh" as the name for the superh arch. there was already some inconsistency internally in musl: the dynamic linker was searching for "ld-musl-sh.path" as its path file despite its own name being "ld-musl-superh.so.1". there was some sentiment in both directions as to how to resolve the inconsistency, but overall "sh" was favored.
2014-02-24add missing sub files for mipsel-sf to use softfloat codeRich Felker-0/+2
the build system has no automatic way to know this code applies to both big (default) and little endian variants, so explicit .sub files are needed.
2014-02-24mips: add mips-sf subarch support (soft-float)Szabolcs Nagy-0/+52
Userspace emulated floating-point (gcc -msoft-float) is not compatible with the default mips abi (assumes an FPU or in kernel emulation of it). Soft vs hard float abi should not be mixed, __mips_soft_float is checked in musl's configure script and there is no runtime check. The -sf subarch does not save/restore floating-point registers in setjmp/longjmp and only provides dummy fenv implementation.
2014-02-23superh portBobby Bingham-0/+51
2014-02-23import vanilla x86_64 code as x32rofl0r-0/+44
2012-12-05remove fenv saving/loading code from setjmp/longjmp on armRich Felker-4/+0
the issue is identical to the recent commit fixing the mips versions: despite other implementations doing this, it conflicts with the requirements of ISO C and it's a waste of time and code size.
2012-12-05remove mips setjmp/longjmp code to save/restore fenvRich Felker-5/+1
nothing in the standard requires or even allows the fenv state to be restored by longjmp. restoring the exception flags is not such a big deal since it's probably valid to clobber them completely, but restoring the rounding mode yields an observable side effect not sanctioned by ISO C. saving/restoring it also wastes a few cycles and 16 bytes of code. as for historical behavior, reportedly SGI IRIX did save/restore fenv, and this is where glibc and uClibc got the behavior from. a few other systems save/restore it too (on archs other than mips), even though this is apparently wrong. further details are documented here: http://www-personal.umich.edu/~williams/archive/computation/setjmp-fpmode.html as musl aims for standards conformance rather than coddling historical programs expecting non-conforming behavior, and as it's unlikely that any historical programs actually depend on the incorrect behavior (such programs would break on other archs, anyway), I'm making the change not to save/restore fenv on mips.
2012-11-23fix powerpc setjmp/longjmp to save/restore float regs; enlarge/align jmp_bufRich Felker-0/+36
2012-11-14fix indention with spaces in powerpc asmRich Felker-10/+10
2012-11-13PPC port cleaned up, static linking works well now.rofl0r-35/+87
2012-11-13import preliminary ppc work by rdp.Richard Pennington-0/+35
2012-09-29microblaze portRich Felker-0/+58
based on initial work by rdp, with heavy modifications. some features including threads are untested because qemu app-level emulation seems to be broken and I do not have a proper system image for testing.
2012-08-05floating point support for arm setjmp/longjmpRich Felker-2/+54
not heavily tested, but at least they don't seem to break anything on soft float targets with or without coprocessors. they check the auxv AT_HWCAP flags to determine which coprocessor, if any, is available.
2012-07-27optimize arm setjmp/longjmp register saving/loadingRich Felker-6/+2
the original code was wrongly based on how it would be done in thumb mode, but that's not needed because musl's asm only targets arm.
2012-07-22add floating point register saving/restoring to mips setjmp/longjmpRich Felker-1/+29
also fix the alignment of jmp_buf to meet the abi. linux always emulates fpu on mips if it's not present, so enabling this code unconditionally is "safe" but may be slow. in the long term it may be preferable to find a way to disable it on soft float builds.
2012-07-11initial version of mips (o32) port, based on work by Richard Pennington (rdp)Rich Felker-0/+50
basically, this version of the code was obtained by starting with rdp's work from his ellcc source tree, adapting it to musl's build system and coding style, auditing the bits headers for discrepencies with kernel definitions or glibc/LSB ABI or large file issues, fixing up incompatibility with the old binutils from aboriginal linux, and adding some new special cases to deal with the oddities of sigaction and pipe syscall interfaces on mips. at present, minimal test programs work, but some interfaces are broken or missing. threaded programs probably will not link.
2012-05-05update license of njk contributed code (x86_64 asm)Rich Felker-2/+2
these changes are based on the following communication via email: "I hereby grant that all of the code I have contributed to musl on or before April 23, 2012 may be licensed under the terms of the following MIT license: Copyright (c) 2011-2012 Nicholas J. Kain Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE."
2011-09-18initial commit of the arm portRich Felker-0/+32
this port assumes eabi calling conventions, eabi linux syscall convention, and presence of the kernel helpers at 0xffff0f?0 needed for threads support. otherwise it makes very few assumptions, and the code should work even on armv4 without thumb support, as well as on systems with thumb interworking. the bits headers declare this a little endian system, but as far as i can tell the code should work equally well on big endian. some small details are probably broken; so far, testing has been limited to qemu/aboriginal linux.
2011-06-14restore use of .type in asm, but use modern @function (vs %function)Rich Felker-0/+10
this seems to be necessary to make the linker accept the functions in a shared library (perhaps to generate PLT entries?) strictly speaking libc-internal asm should not need it. i might clean that up later.
2011-06-13remove all .size and .type directives for functions from the asmRich Felker-20/+0
these are useless and have caused problems for users trying to build with non-gnu tools like tcc's assembler.