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| author | Rich Felker <dalias@aerifal.cx> | 2026-03-21 15:14:41 -0400 |
|---|---|---|
| committer | Rich Felker <dalias@aerifal.cx> | 2026-03-21 15:14:41 -0400 |
| commit | 3df932bc33a5f1ae56636abfd4241e34d5c648db (patch) | |
| tree | faeb59bbf713b705057d38a7d375ce277c616186 /src | |
| parent | 1969500402bc4f80452e1c066401223a3c998f54 (diff) | |
| download | musl-3df932bc33a5f1ae56636abfd4241e34d5c648db.tar.gz | |
fix condition for riscv{32,64} non-stup fenv
whether fenv is supported depends on the ABI, not whether the target
cpu ISA level has floating point support.
Diffstat (limited to 'src')
| -rw-r--r-- | src/fenv/riscv32/fenv-sf.c | 2 | ||||
| -rw-r--r-- | src/fenv/riscv32/fenv.S | 2 | ||||
| -rw-r--r-- | src/fenv/riscv64/fenv-sf.c | 2 | ||||
| -rw-r--r-- | src/fenv/riscv64/fenv.S | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/src/fenv/riscv32/fenv-sf.c b/src/fenv/riscv32/fenv-sf.c index ecd3cb5c..670a77a2 100644 --- a/src/fenv/riscv32/fenv-sf.c +++ b/src/fenv/riscv32/fenv-sf.c @@ -1,3 +1,3 @@ -#ifndef __riscv_flen +#ifdef __riscv_float_abi_soft #include "../fenv.c" #endif diff --git a/src/fenv/riscv32/fenv.S b/src/fenv/riscv32/fenv.S index 0ea78bf9..1deab07f 100644 --- a/src/fenv/riscv32/fenv.S +++ b/src/fenv/riscv32/fenv.S @@ -1,4 +1,4 @@ -#ifdef __riscv_flen +#ifndef __riscv_float_abi_soft .global feclearexcept .type feclearexcept, %function diff --git a/src/fenv/riscv64/fenv-sf.c b/src/fenv/riscv64/fenv-sf.c index ecd3cb5c..670a77a2 100644 --- a/src/fenv/riscv64/fenv-sf.c +++ b/src/fenv/riscv64/fenv-sf.c @@ -1,3 +1,3 @@ -#ifndef __riscv_flen +#ifdef __riscv_float_abi_soft #include "../fenv.c" #endif diff --git a/src/fenv/riscv64/fenv.S b/src/fenv/riscv64/fenv.S index 0ea78bf9..1deab07f 100644 --- a/src/fenv/riscv64/fenv.S +++ b/src/fenv/riscv64/fenv.S @@ -1,4 +1,4 @@ -#ifdef __riscv_flen +#ifndef __riscv_float_abi_soft .global feclearexcept .type feclearexcept, %function |