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authorrofl0r <retnyg@gmx.net>2012-11-09 23:36:55 +0100
committerrofl0r <retnyg@gmx.net>2012-11-13 19:12:25 +0100
commit1c8eb8bad791fe9d01d0d4ab77882db634fa933d (patch)
treed3faf83663c1383f7ea16a0e6c68b3e2f4cc968a /src/setjmp/powerpc
parent7669d1e334e6b96455eece78da43bf830b93d697 (diff)
downloadmusl-1c8eb8bad791fe9d01d0d4ab77882db634fa933d.tar.gz
PPC port cleaned up, static linking works well now.
Diffstat (limited to 'src/setjmp/powerpc')
-rw-r--r--src/setjmp/powerpc/longjmp.s47
-rw-r--r--src/setjmp/powerpc/setjmp.s40
2 files changed, 87 insertions, 0 deletions
diff --git a/src/setjmp/powerpc/longjmp.s b/src/setjmp/powerpc/longjmp.s
new file mode 100644
index 00000000..e3740901
--- /dev/null
+++ b/src/setjmp/powerpc/longjmp.s
@@ -0,0 +1,47 @@
+ .global _longjmp
+ .global longjmp
+ .type _longjmp,@function
+ .type longjmp,@function
+_longjmp:
+longjmp:
+# void longjmp(jmp_buf env, int val);
+# put val into return register and restore the env saved in setjmp
+# if val(r4) is 0, put 1 there.
+ # 0) move old return address into r0
+ lwz 0, 0(3)
+ # 1) put it into link reg
+ mtlr 0
+ #2 ) restore stack ptr
+ lwz 1, 4(3)
+ #3) restore control reg
+ lwz 0, 8(3)
+ mtcr 0
+ #4) restore r14-r31
+ lwz 14, 12(3)
+ lwz 15, 16(3)
+ lwz 16, 20(3)
+ lwz 17, 24(3)
+ lwz 18, 28(3)
+ lwz 19, 32(3)
+ lwz 20, 36(3)
+ lwz 21, 40(3)
+ lwz 22, 44(3)
+ lwz 23, 48(3)
+ lwz 24, 52(3)
+ lwz 25, 56(3)
+ lwz 26, 60(3)
+ lwz 27, 64(3)
+ lwz 28, 68(3)
+ lwz 29, 72(3)
+ lwz 30, 76(3)
+ lwz 31, 80(3)
+ #5) put val into return reg r3
+ mr 3, 4
+
+ #6) check if return value is 0, make it 1 in that case
+ cmpwi cr7, 4, 0
+ bne cr7, 1f
+ li 3, 1
+1:
+ blr
+
diff --git a/src/setjmp/powerpc/setjmp.s b/src/setjmp/powerpc/setjmp.s
new file mode 100644
index 00000000..27c975e4
--- /dev/null
+++ b/src/setjmp/powerpc/setjmp.s
@@ -0,0 +1,40 @@
+ .global __setjmp
+ .global _setjmp
+ .global setjmp
+ .type __setjmp,@function
+ .type _setjmp,@function
+ .type setjmp,@function
+__setjmp:
+_setjmp:
+setjmp:
+ # 0) store IP int 0, then into the jmpbuf pointed to by r3 (first arg)
+ mflr 0
+ stw 0, 0(3)
+ # 1) store reg1 (SP)
+ stw 1, 4(3)
+ # 2) store cr
+ mfcr 0
+ stw 0, 8(3)
+ # 3) store r14-31
+ stw 14, 12(3)
+ stw 15, 16(3)
+ stw 16, 20(3)
+ stw 17, 24(3)
+ stw 18, 28(3)
+ stw 19, 32(3)
+ stw 20, 36(3)
+ stw 21, 40(3)
+ stw 22, 44(3)
+ stw 23, 48(3)
+ stw 24, 52(3)
+ stw 25, 56(3)
+ stw 26, 60(3)
+ stw 27, 64(3)
+ stw 28, 68(3)
+ stw 29, 72(3)
+ stw 30, 76(3)
+ stw 31, 80(3)
+ # 4) set return value to 0
+ li 3, 0
+ # 5) return
+ blr