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2021-09-23add SPE FPU support to powerpc-sfRich Felker-1/+1
When the soft-float ABI for PowerPC was added in commit 5a92dd95c77cee81755f1a441ae0b71e3ae2bcdb, with Freescale cpus using the alternative SPE FPU as the main use case, it was noted that we could probably support hard float on them, but that it would involve determining some difficult ABI constraints. This commit is the completion of that work. The Power-Arch-32 ABI supplement defines the ABI profiles, and indeed ATR-SPE is built on ATR-SOFT-FLOAT. But setjmp/longjmp compatibility are problematic for the same reason they're problematic on ARM, where optional float-related parts of the register file are "call-saved if present". This requires testing __hwcap, which is now done. In keeping with the existing powerpc-sf subarch definition, which did not have fenv, the fenv macros are not defined for SPE and the SPEFSCR control register is left (and assumed to start in) the default mode.
2016-03-06add powerpc soft-float supportFelix Fietkau-0/+5
Some PowerPC CPUs (e.g. Freescale MPC85xx) have a completely different instruction set for floating point operations (SPE). Executing regular PowerPC floating point instructions results in "Illegal instruction" errors. Make it possible to run these devices in soft-float mode.
2012-11-18add missing const on powerpc FE_DFL_ENVRich Felker-1/+1
2012-11-18fenv support for ppc, untestedRich Felker-7/+28
based on code sent to the mailing list by nsz, with minor changes.
2012-11-13PPC port cleaned up, static linking works well now.rofl0r-0/+10