4 files changed, 35 insertions, 15 deletions
diff --git a/src/thread/aarch64/__set_thread_area.c b/src/thread/aarch64/__set_thread_area.c
new file mode 100644
index 00000000..2ec788e8
--- /dev/null
+++ b/src/thread/aarch64/__set_thread_area.c
@@ -0,0 +1,27 @@
+#include <elf.h>
+#include "libc.h"
+
+#define BITRANGE(a,b) (2*(1UL<<(b))-(1UL<<(a)))
+
+int __set_thread_area(void *p)
+{
+	__asm__ __volatile__ ("msr tpidr_el0,%0" : : "r"(p) : "memory");
+
+	/* Mask off hwcap bits for SME and unknown future features. This is
+	 * necessary because SME is not safe to use without libc support for
+	 * it, and we do not (yet) have such support. */
+	for (size_t *v = libc.auxv; *v; v+=2) {
+		if (v[0]==AT_HWCAP) {
+			v[1] &= ~BITRANGE(42,63); /* 42-47 are SME */
+		} else if (v[0]==AT_HWCAP2) {
+			v[1] &= ~(BITRANGE(23,30)
+			        | BITRANGE(37,42)
+			        | BITRANGE(57,62));
+		} else if (v[0]==AT_HWCAP3 || v[0]==AT_HWCAP4) {
+			v[0] = AT_IGNORE;
+			v[1] = 0;
+		}
+	}
+
+	return 0;
+}
diff --git a/src/thread/aarch64/__set_thread_area.s b/src/thread/aarch64/__set_thread_area.s
deleted file mode 100644
index fd0df34b..00000000
--- a/src/thread/aarch64/__set_thread_area.s
+++ /dev/null
@@ -1,7 +0,0 @@
-.global __set_thread_area
-.hidden __set_thread_area
-.type   __set_thread_area,@function
-__set_thread_area:
-	msr tpidr_el0,x0
-	mov w0,#0
-	ret
diff --git a/src/thread/aarch64/clone.s b/src/thread/aarch64/clone.s
index 9ac272bd..aff8155b 100644
--- a/src/thread/aarch64/clone.s
+++ b/src/thread/aarch64/clone.s
@@ -24,7 +24,7 @@ __clone:
 	// parent
 	ret
 	// child
-1:	mov fp, 0
+1:	mov x29, 0
 	ldp x1,x0,[sp],#16
 	blr x1
 	mov x8,#93 // SYS_exit
diff --git a/src/thread/s390x/__tls_get_offset.s b/src/thread/s390x/__tls_get_offset.s
index 405f118b..056c9110 100644
--- a/src/thread/s390x/__tls_get_offset.s
+++ b/src/thread/s390x/__tls_get_offset.s
@@ -1,17 +1,17 @@
 	.global __tls_get_offset
 	.type __tls_get_offset,%function
 __tls_get_offset:
-	ear   %r0, %a0
-	sllg  %r0, %r0, 32
-	ear   %r0, %a1
+	ear   %r3, %a0
+	sllg  %r3, %r3, 32
+	ear   %r3, %a1
 
 	la    %r1, 0(%r2, %r12)
 
-	lg    %r3, 0(%r1)
-	sllg  %r4, %r3, 3
-	lg    %r5, 8(%r0)
+	lg    %r0, 0(%r1)
+	sllg  %r4, %r0, 3
+	lg    %r5, 8(%r3)
 	lg    %r2, 0(%r4, %r5)
 	ag    %r2, 8(%r1)
-	sgr   %r2, %r0
+	sgr   %r2, %r3
 
 	br    %r14