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| author | Alex Rønne Petersen <alex@alexrp.com> | 2024-06-29 04:04:34 +0200 |
|---|---|---|
| committer | Rich Felker <dalias@aerifal.cx> | 2025-08-16 23:17:56 -0400 |
| commit | 0b86d60badad6a69b37fc06d18b5763fbbf47b58 (patch) | |
| tree | 7a67e3cc3bb31c9eb0af01135c6de1e6e941232d /src/setjmp/riscv32/setjmp.S | |
| parent | f6944eb3c4ce1c97dc39dc36d32390dc9f70b67b (diff) | |
| download | musl-0b86d60badad6a69b37fc06d18b5763fbbf47b58.tar.gz | |
per the psABI, floating point register contents beyond the register
size of the targeted ABI variant are never call-saved, so no
hwcap-conditional logic is needed here and the assembly-time
conditions are based purely on ABI variant macros, not the targeted
ISA level.
Diffstat (limited to 'src/setjmp/riscv32/setjmp.S')
| -rw-r--r-- | src/setjmp/riscv32/setjmp.S | 30 |
1 files changed, 18 insertions, 12 deletions
diff --git a/src/setjmp/riscv32/setjmp.S b/src/setjmp/riscv32/setjmp.S index 8a75cf55..5a1a41ef 100644 --- a/src/setjmp/riscv32/setjmp.S +++ b/src/setjmp/riscv32/setjmp.S @@ -23,18 +23,24 @@ setjmp: sw ra, 52(a0) #ifndef __riscv_float_abi_soft - fsd fs0, 56(a0) - fsd fs1, 64(a0) - fsd fs2, 72(a0) - fsd fs3, 80(a0) - fsd fs4, 88(a0) - fsd fs5, 96(a0) - fsd fs6, 104(a0) - fsd fs7, 112(a0) - fsd fs8, 120(a0) - fsd fs9, 128(a0) - fsd fs10, 136(a0) - fsd fs11, 144(a0) +#ifdef __riscv_float_abi_double +#define FSX fsd +#else +#define FSX fsw +#endif + + FSX fs0, 56(a0) + FSX fs1, 64(a0) + FSX fs2, 72(a0) + FSX fs3, 80(a0) + FSX fs4, 88(a0) + FSX fs5, 96(a0) + FSX fs6, 104(a0) + FSX fs7, 112(a0) + FSX fs8, 120(a0) + FSX fs9, 128(a0) + FSX fs10, 136(a0) + FSX fs11, 144(a0) #endif li a0, 0 |