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authorAndre McCurdy <armccurdy@gmail.com>2019-09-13 11:44:31 -0700
committerRich Felker <dalias@aerifal.cx>2020-01-16 15:44:26 -0500
commit91e662d1d941215eb024787db5e910dbfb5b169f (patch)
treed3b2506ee656488fd55cdae9923373c2e354a8dd
parent0ff18be20833928064f6eff88e590cea9625f602 (diff)
downloadmusl-master.tar.gz
add thumb2 support to arm assembler memcpyHEADmaster
For Thumb2 compatibility, replace two instances of a single instruction "orr with a variable shift" with the two instruction equivalent. Neither of the replacements are in a performance critical loop.
-rw-r--r--src/string/arm/memcpy.c2
-rw-r--r--src/string/arm/memcpy_le.S13
2 files changed, 9 insertions, 6 deletions
diff --git a/src/string/arm/memcpy.c b/src/string/arm/memcpy.c
index f703c9bd..041614f4 100644
--- a/src/string/arm/memcpy.c
+++ b/src/string/arm/memcpy.c
@@ -1,3 +1,3 @@
-#if __ARMEB__ || __thumb__
+#if __ARMEB__
#include "../memcpy.c"
#endif
diff --git a/src/string/arm/memcpy_le.S b/src/string/arm/memcpy_le.S
index 9cfbcb2a..7b35d305 100644
--- a/src/string/arm/memcpy_le.S
+++ b/src/string/arm/memcpy_le.S
@@ -1,4 +1,4 @@
-#if !__ARMEB__ && !__thumb__
+#if !__ARMEB__
/*
* Copyright (C) 2008 The Android Open Source Project
@@ -40,8 +40,9 @@
* This file has been modified from the original for use in musl libc.
* The main changes are: addition of .type memcpy,%function to make the
* code safely callable from thumb mode, adjusting the return
- * instructions to be compatible with pre-thumb ARM cpus, and removal
- * of prefetch code that is not compatible with older cpus.
+ * instructions to be compatible with pre-thumb ARM cpus, removal of
+ * prefetch code that is not compatible with older cpus and support for
+ * building as thumb 2.
*/
.syntax unified
@@ -241,7 +242,8 @@ non_congruent:
beq 2f
ldr r5, [r1], #4
sub r2, r2, #4
- orr r4, r3, r5, lsl lr
+ mov r4, r5, lsl lr
+ orr r4, r4, r3
mov r3, r5, lsr r12
str r4, [r0], #4
cmp r2, #4
@@ -348,7 +350,8 @@ less_than_thirtytwo:
1: ldr r5, [r1], #4
sub r2, r2, #4
- orr r4, r3, r5, lsl lr
+ mov r4, r5, lsl lr
+ orr r4, r4, r3
mov r3, r5, lsr r12
str r4, [r0], #4
cmp r2, #4