From 8c0a3d9e5c169fc9d0f246ab59362b658b029ad7 Mon Sep 17 00:00:00 2001
From: Rich Felker <dalias@aerifal.cx>
Date: Sat, 29 Sep 2012 01:05:31 -0400
Subject: microblaze port

based on initial work by rdp, with heavy modifications. some features
including threads are untested because qemu app-level emulation seems
to be broken and I do not have a proper system image for testing.
---
 src/setjmp/microblaze/longjmp.s | 29 +++++++++++++++++++++++++++++
 src/setjmp/microblaze/setjmp.s  | 29 +++++++++++++++++++++++++++++
 2 files changed, 58 insertions(+)
 create mode 100644 src/setjmp/microblaze/longjmp.s
 create mode 100644 src/setjmp/microblaze/setjmp.s

(limited to 'src/setjmp')

diff --git a/src/setjmp/microblaze/longjmp.s b/src/setjmp/microblaze/longjmp.s
new file mode 100644
index 00000000..c0760288
--- /dev/null
+++ b/src/setjmp/microblaze/longjmp.s
@@ -0,0 +1,29 @@
+.global _longjmp
+.global longjmp
+.type   _longjmp,@function
+.type   longjmp,@function
+_longjmp:
+longjmp:
+	addi    r3, r6, 0
+	bnei    r3, 1f
+	addi    r3, r3, 1
+1:      lwi     r1,  r5, 0
+	lwi     r15, r5, 4
+	lwi     r2,  r5, 8
+	lwi     r13, r5, 12
+	lwi     r18, r5, 16
+	lwi     r19, r5, 20
+	lwi     r20, r5, 24
+	lwi     r21, r5, 28
+	lwi     r22, r5, 32
+	lwi     r23, r5, 36
+	lwi     r24, r5, 40
+	lwi     r25, r5, 44
+	lwi     r26, r5, 48
+	lwi     r27, r5, 52
+	lwi     r28, r5, 56
+	lwi     r29, r5, 60
+	lwi     r30, r5, 64
+	lwi     r31, r5, 68
+	rtsd    r15, 8
+	nop
diff --git a/src/setjmp/microblaze/setjmp.s b/src/setjmp/microblaze/setjmp.s
new file mode 100644
index 00000000..f39468a5
--- /dev/null
+++ b/src/setjmp/microblaze/setjmp.s
@@ -0,0 +1,29 @@
+.global __setjmp
+.global _setjmp
+.global setjmp
+.type __setjmp,@function
+.type _setjmp,@function
+.type setjmp,@function
+__setjmp:
+_setjmp:
+setjmp:
+	swi     r1,  r5, 0
+	swi     r15, r5, 4
+	swi     r2,  r5, 8
+	swi     r13, r5, 12
+	swi     r18, r5, 16
+	swi     r19, r5, 20
+	swi     r20, r5, 24
+	swi     r21, r5, 28
+	swi     r22, r5, 32
+	swi     r23, r5, 36
+	swi     r24, r5, 30
+	swi     r25, r5, 44
+	swi     r26, r5, 48
+	swi     r27, r5, 52
+	swi     r28, r5, 56
+	swi     r29, r5, 60
+	swi     r30, r5, 64
+	swi     r31, r5, 68
+	rtsd    r15, 8
+	ori     r3, r0, 0
-- 
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