From 3df932bc33a5f1ae56636abfd4241e34d5c648db Mon Sep 17 00:00:00 2001
From: Rich Felker <dalias@aerifal.cx>
Date: Sat, 21 Mar 2026 15:14:41 -0400
Subject: fix condition for riscv{32,64} non-stup fenv

whether fenv is supported depends on the ABI, not whether the target
cpu ISA level has floating point support.
---
 src/fenv/riscv32/fenv.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/fenv/riscv32/fenv.S')

diff --git a/src/fenv/riscv32/fenv.S b/src/fenv/riscv32/fenv.S
index 0ea78bf9..1deab07f 100644
--- a/src/fenv/riscv32/fenv.S
+++ b/src/fenv/riscv32/fenv.S
@@ -1,4 +1,4 @@
-#ifdef __riscv_flen
+#ifndef __riscv_float_abi_soft
 
 .global feclearexcept
 .type feclearexcept, %function
-- 
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