From a6b0170a7f51fdea9beec57ae794221290af232b Mon Sep 17 00:00:00 2001 From: Szabolcs Nagy Date: Sun, 18 Aug 2013 20:08:18 +0000 Subject: fix fenv exception functions to mask their argument fesetround.c is a wrapper to do the arch independent argument check (on archs where rounding mode is not stored in 2 bits __fesetround still has to check its arguments) on powerpc fe*except functions do not accept the extra invalid flags of its fpscr register the useless FENV_ACCESS pragma was removed from feupdateenv --- src/fenv/armhf/fenv.s | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'src/fenv/armhf/fenv.s') diff --git a/src/fenv/armhf/fenv.s b/src/fenv/armhf/fenv.s index ee81b3d5..26ac87e1 100644 --- a/src/fenv/armhf/fenv.s +++ b/src/fenv/armhf/fenv.s @@ -5,9 +5,9 @@ fegetround: and r0, r0, #0xc00000 bx lr -.global fesetround -.type fesetround,%function -fesetround: +.global __fesetround +.type __fesetround,%function +__fesetround: mrc p10, 7, r3, cr1, cr0, 0 bic r3, r3, #0xc00000 orr r3, r3, r0 @@ -18,6 +18,7 @@ fesetround: .global fetestexcept .type fetestexcept,%function fetestexcept: + and r0, r0, #0x1f mrc p10, 7, r3, cr1, cr0, 0 and r0, r0, r3 bx lr @@ -25,6 +26,7 @@ fetestexcept: .global feclearexcept .type feclearexcept,%function feclearexcept: + and r0, r0, #0x1f mrc p10, 7, r3, cr1, cr0, 0 bic r3, r3, r0 mcr p10, 7, r3, cr1, cr0, 0 @@ -34,6 +36,7 @@ feclearexcept: .global feraiseexcept .type feraiseexcept,%function feraiseexcept: + and r0, r0, #0x1f mrc p10, 7, r3, cr1, cr0, 0 orr r3, r3, r0 mcr p10, 7, r3, cr1, cr0, 0 -- cgit v1.2.1