From 01d9fe4d9f7cce7a6dbaece0e2e405a2e3279244 Mon Sep 17 00:00:00 2001 From: Stefan O'Rear Date: Thu, 3 Sep 2020 05:40:29 -0400 Subject: riscv32: add arch headers These are mostly copied from riscv64. _Addr and _Reg had to become int to match compiler-controlled parts of the ABI (result type of sizeof, etc.). There is no kernel stat struct; the userspace stat matches glibc in the sizes and offsets of all fields (including glibc's __dev_t __pad1). The jump buffer is 12 words larger to account for 12 saved double-precision floats; additionally it should be 64-bit aligned to save doubles. The syscall list was significantly revised by deleting all time32 and pre-statx syscalls, and renaming several syscalls that have different names depending on __BITS_PER_LONG, notably mmap2 and _llseek. futex was added as an alias to futex_time64 since it is widely used by software which does not pass time arguments. --- arch/riscv32/atomic_arch.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 arch/riscv32/atomic_arch.h (limited to 'arch/riscv32/atomic_arch.h') diff --git a/arch/riscv32/atomic_arch.h b/arch/riscv32/atomic_arch.h new file mode 100644 index 00000000..4d418f63 --- /dev/null +++ b/arch/riscv32/atomic_arch.h @@ -0,0 +1,21 @@ +#define a_barrier a_barrier +static inline void a_barrier() +{ + __asm__ __volatile__ ("fence rw,rw" : : : "memory"); +} + +#define a_cas a_cas +static inline int a_cas(volatile int *p, int t, int s) +{ + int old, tmp; + __asm__ __volatile__ ( + "\n1: lr.w.aqrl %0, (%2)\n" + " bne %0, %3, 1f\n" + " sc.w.aqrl %1, %4, (%2)\n" + " bnez %1, 1b\n" + "1:" + : "=&r"(old), "=&r"(tmp) + : "r"(p), "r"((long)t), "r"((long)s) + : "memory"); + return old; +} -- cgit v1.2.1