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authorStefan Kristiansson <stefan.kristiansson@saunalahti.fi>2014-07-17 22:09:10 +0300
committerRich Felker <dalias@aerifal.cx>2014-07-18 14:10:23 -0400
commit200d15479c0bc48471ee7b8e538ce33af990f82e (patch)
tree864cc38895b9277384ed3a956f4ad324de2c4455 /crt
parent7bece9c2095ee81f14b1088f6b0ba2f37fecb283 (diff)
downloadmusl-200d15479c0bc48471ee7b8e538ce33af990f82e.tar.gz
add or1k (OpenRISC 1000) architecture port
With the exception of a fenv implementation, the port is fully featured. The port has been tested in or1ksim, the golden reference functional simulator for OpenRISC 1000. It passes all libc-test tests (except the math tests that requires a fenv implementation). The port assumes an or1k implementation that has support for atomic instructions (l.lwa/l.swa). Although it passes all the libc-test tests, the port is still in an experimental state, and has yet experienced very little 'real-world' use.
Diffstat (limited to 'crt')
-rw-r--r--crt/or1k/crti.s11
-rw-r--r--crt/or1k/crtn.s9
2 files changed, 20 insertions, 0 deletions
diff --git a/crt/or1k/crti.s b/crt/or1k/crti.s
new file mode 100644
index 00000000..7e741459
--- /dev/null
+++ b/crt/or1k/crti.s
@@ -0,0 +1,11 @@
+.section .init
+.global _init
+_init:
+ l.addi r1,r1,-4
+ l.sw 0(r1),r9
+
+.section .fini
+.global _fini
+_fini:
+ l.addi r1,r1,-4
+ l.sw 0(r1),r9
diff --git a/crt/or1k/crtn.s b/crt/or1k/crtn.s
new file mode 100644
index 00000000..4185a027
--- /dev/null
+++ b/crt/or1k/crtn.s
@@ -0,0 +1,9 @@
+.section .init
+ l.lwz r9,0(r1)
+ l.jr r9
+ l.addi r1,r1,4
+
+.section .fini
+ l.lwz r9,0(r1)
+ l.jr r9
+ l.addi r1,r1,4