path: root/arch/powerpc/pthread_arch.h
diff options
authorRich Felker <>2015-10-15 12:08:51 -0400
committerRich Felker <>2015-10-15 12:08:51 -0400
commit92637bb0d8f13940aebd2a8116cc935c3e7d8266 (patch)
treed3c5f18bda12af14834b0d2eeb484c24e80e3cf0 /arch/powerpc/pthread_arch.h
parent74483c5955a632af5d9a4783cc2b541764450551 (diff)
prevent reordering of or1k and powerpc thread pointer loads
other archs use asm for the thread pointer load, so making that asm volatile is sufficient to inform the compiler that it has a "side effect" (crashing or giving the wrong result if the thread pointer was not yet initialized) that prevents reordering. however, powerpc and or1k have dedicated general purpose registers for the thread pointer and did not need to use any asm to access it; instead, "local register variables with a specified register" were used. however, there is no specification for ordering constraints on this type of usage, and presumably use of the thread pointer could be reordered across its initialization. to impose an ordering, I have added empty volatile asm blocks that produce the "local register variable with a specified register" as an output constraint.
Diffstat (limited to 'arch/powerpc/pthread_arch.h')
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/pthread_arch.h b/arch/powerpc/pthread_arch.h
index 1cbfc223..bb7405d1 100644
--- a/arch/powerpc/pthread_arch.h
+++ b/arch/powerpc/pthread_arch.h
@@ -5,6 +5,7 @@ static inline struct pthread *__pthread_self()
__asm__ __volatile__ ("mr %0, 2" : "=r"(tp) : : );
register char *tp __asm__("r2");
+ __asm__ __volatile__ ("" : "=r" (tp) );
return (pthread_t)(tp - 0x7000 - sizeof(struct pthread));