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authorRich Felker <dalias@aerifal.cx>2014-04-14 23:41:49 -0400
committerRich Felker <dalias@aerifal.cx>2014-04-14 23:41:49 -0400
commit3933fdd5001cc72cb1ea8bb92bbe536b8b601504 (patch)
tree281c79dd4a6ea846193d1f28ca48222c54da9146 /arch/arm
parent83c98aac4c43f9571e8f92a1c795afe02c237d4b (diff)
downloadmusl-3933fdd5001cc72cb1ea8bb92bbe536b8b601504.tar.gz
use dmb barrier instruction for atomics on arm v7
aside from potentially offering better performance, this change is needed since the old coprocessor-based approach to barriers is deprecated in arm v7, and some compilers/assemblers issue errors when using the deprecated instruction for v7 targets.
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/atomic.h11
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/arm/atomic.h b/arch/arm/atomic.h
index 50ad9478..d8f64843 100644
--- a/arch/arm/atomic.h
+++ b/arch/arm/atomic.h
@@ -25,17 +25,24 @@ static inline int a_ctz_64(uint64_t x)
#if __ARM_ARCH_6__ || __ARM_ARCH_6K__ || __ARM_ARCH_6ZK__ \
|| __ARM_ARCH_7A__ || __ARM_ARCH_7R__ \
|| __ARM_ARCH >= 7
+
+#if __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
+#define MEM_BARRIER "dmb ish"
+#else
+#define MEM_BARRIER "mcr p15,0,r0,c7,c10,5"
+#endif
+
static inline int __k_cas(int t, int s, volatile int *p)
{
int ret;
__asm__(
- " mcr p15,0,r0,c7,c10,5\n"
+ " " MEM_BARRIER "\n"
"1: ldrex %0,%3\n"
" subs %0,%0,%1\n"
" strexeq %0,%2,%3\n"
" teqeq %0,#1\n"
" beq 1b\n"
- " mcr p15,0,r0,c7,c10,5\n"
+ " " MEM_BARRIER "\n"
: "=&r"(ret)
: "r"(t), "r"(s), "Q"(*p)
: "memory", "cc" );