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authorRich Felker <dalias@aerifal.cx>2015-11-09 22:36:38 -0500
committerRich Felker <dalias@aerifal.cx>2015-11-09 22:36:38 -0500
commit9f290a49bf9ee247d540d3c83875288a7991699c (patch)
treed9904f2b9698083ae64c122849a3dc3279f5856a /arch/arm/src/arm/atomics.s
parentcf40375e8fd14fc02a850af90b145d324d0381b5 (diff)
downloadmusl-9f290a49bf9ee247d540d3c83875288a7991699c.tar.gz
remove non-working pre-armv4t support from arm asm
the idea of the three-instruction sequence being removed was to be able to return to thumb code when used on armv4t+ from a thumb caller, but also to be able to run on armv4 without the bx instruction available (in which case the low bit of lr would always be 0). however, without compiler support for generating such a sequence from C code, which does not exist and which there is unlikely to be interest in implementing, there is little point in having it in the asm, and it would likely be easier to add pre-armv4t support via enhanced linker handling of R_ARM_V4BX than at the compiler level. removing this code simplifies adding support for building libc in thumb2-only form (for cortex-m).
Diffstat (limited to 'arch/arm/src/arm/atomics.s')
-rw-r--r--arch/arm/src/arm/atomics.s6
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/arm/src/arm/atomics.s b/arch/arm/src/arm/atomics.s
index f241cc02..ecf3f05a 100644
--- a/arch/arm/src/arm/atomics.s
+++ b/arch/arm/src/arm/atomics.s
@@ -11,8 +11,6 @@ __a_barrier:
.global __a_barrier_dummy
.hidden __a_barrier_dummy
__a_barrier_dummy:
- tst lr,#1
- moveq pc,lr
bx lr
.global __a_barrier_oldkuser
.hidden __a_barrier_oldkuser
@@ -24,8 +22,6 @@ __a_barrier_oldkuser:
mov lr,pc
mov pc,ip
pop {r0,r1,r2,r3,ip,lr}
- tst lr,#1
- moveq pc,lr
bx lr
.global __a_barrier_v6
.hidden __a_barrier_v6
@@ -53,8 +49,6 @@ __a_cas_dummy:
ldr r0,[r2]
subs r0,r3,r0
streq r1,[r2]
- tst lr,#1
- moveq pc,lr
bx lr
.global __a_cas_v6
.hidden __a_cas_v6