|author||Rich Felker <firstname.lastname@example.org>||2016-12-18 19:38:53 -0500|
|committer||Rich Felker <email@example.com>||2016-12-19 21:21:08 -0500|
rework arm atomic/tp backends to be thumb-compatible and fdpic-ready
three problems are addressed: - use of pc arithmetic, which was difficult if not impossible to make correct in thumb mode on all models, so that relative rather than absolute pointers to the backends could be used. this was designed back when there was no coherent model for the early stages of the dynamic linker before relocations, and is no longer necessary. - assumption that data (the relative pointers to the backends) can be accessed at a constant displacement from the code. this will not be possible on future fdpic subarchs (for cortex-m), so move responsibility for loading the backend code address to the caller. - hard-coded arm opcodes using the .word directive. instead, use the .arch directive to work around the assembler's refusal to assemble instructions not available (or in some cases, available but just considered deprecated) in the target isa level. the obscure v6t2 arch is used for v6 code so as to (1) allow generation of thumb2 output if -mthumb is active, and (2) avoid warnings/errors for mcr barriers that clang would produce if we just set arch to v7-a. in addition, the __aeabi_read_tp function is moved out of the inner workings and implemented as an asm wrapper around a C function, so that asm code does not need to read global data. the asm wrapper serves to satisfy the ABI calling convention requirements for this function.
Diffstat (limited to 'arch/arm/pthread_arch.h')
1 files changed, 9 insertions, 7 deletions
diff --git a/arch/arm/pthread_arch.h b/arch/arm/pthread_arch.h
index 8b8a7fb6..197752ef 100644
@@ -10,15 +10,17 @@ static inline pthread_t __pthread_self()
-static inline pthread_t __pthread_self()
- char *p;
- __asm__ __volatile__ ( "bl __a_gettp\n\tmov %0,r0" : "=r"(p) : : "cc", "r0", "lr" );
+#if __ARM_ARCH_4__ || __ARM_ARCH_4T__ || __ARM_ARCH == 4
+#define BLX "mov lr,pc\n\tbx"
- register char *p __asm__("r0");
- __asm__ __volatile__ ( "bl __a_gettp" : "=r"(p) : : "cc", "lr" );
+#define BLX "blx"
+static inline pthread_t __pthread_self()
+ extern uintptr_t __attribute__((__visibility__("hidden"))) __a_gettp_ptr;
+ register uintptr_t p __asm__("r0");
+ __asm__ __volatile__ ( BLX " %1" : "=r"(p) : "r"(__a_gettp_ptr) : "cc", "lr" );
return (void *)(p+8-sizeof(struct pthread));