path: root/arch/arm/atomic_arch.h
diff options
authorRich Felker <>2016-12-18 19:38:53 -0500
committerRich Felker <>2016-12-19 21:21:08 -0500
commit29237f7f5c09c436825a7a12b68ab4143b0ebd1f (patch)
tree486acbdd1ea1f652fa79ca2ccba145dc745e7316 /arch/arm/atomic_arch.h
parent9067a3006ea2f84395ab23a1dd30191387312e0c (diff)
rework arm atomic/tp backends to be thumb-compatible and fdpic-ready
three problems are addressed: - use of pc arithmetic, which was difficult if not impossible to make correct in thumb mode on all models, so that relative rather than absolute pointers to the backends could be used. this was designed back when there was no coherent model for the early stages of the dynamic linker before relocations, and is no longer necessary. - assumption that data (the relative pointers to the backends) can be accessed at a constant displacement from the code. this will not be possible on future fdpic subarchs (for cortex-m), so move responsibility for loading the backend code address to the caller. - hard-coded arm opcodes using the .word directive. instead, use the .arch directive to work around the assembler's refusal to assemble instructions not available (or in some cases, available but just considered deprecated) in the target isa level. the obscure v6t2 arch is used for v6 code so as to (1) allow generation of thumb2 output if -mthumb is active, and (2) avoid warnings/errors for mcr barriers that clang would produce if we just set arch to v7-a. in addition, the __aeabi_read_tp function is moved out of the inner workings and implemented as an asm wrapper around a C function, so that asm code does not need to read global data. the asm wrapper serves to satisfy the ABI calling convention requirements for this function.
Diffstat (limited to 'arch/arm/atomic_arch.h')
1 files changed, 14 insertions, 7 deletions
diff --git a/arch/arm/atomic_arch.h b/arch/arm/atomic_arch.h
index 706fa1f2..d6af84d0 100644
--- a/arch/arm/atomic_arch.h
+++ b/arch/arm/atomic_arch.h
@@ -1,5 +1,11 @@
-extern const void *__arm_atomics[3]; /* gettp, cas, barrier */
+#if __ARM_ARCH_4__ || __ARM_ARCH_4T__ || __ARM_ARCH == 4
+#define BLX "mov lr,pc\n\tbx"
+#define BLX "blx"
+extern uintptr_t __attribute__((__visibility__("hidden")))
+ __a_cas_ptr, __a_barrier_ptr;
#if ((__ARM_ARCH_6__ || __ARM_ARCH_6K__ || __ARM_ARCH_6ZK__) && !__thumb__) \
|| __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
@@ -42,11 +48,12 @@ static inline int a_cas(volatile int *p, int t, int s)
register int r0 __asm__("r0") = t;
register int r1 __asm__("r1") = s;
register volatile int *r2 __asm__("r2") = p;
+ register uintptr_t r3 __asm__("r3") = __a_cas_ptr;
int old;
__asm__ __volatile__ (
- "bl __a_cas"
- : "+r"(r0) : "r"(r1), "r"(r2)
- : "memory", "r3", "lr", "ip", "cc" );
+ BLX " r3"
+ : "+r"(r0), "+r"(r3) : "r"(r1), "r"(r2)
+ : "memory", "lr", "ip", "cc" );
if (!r0) return t;
if ((old=*p)!=t) return old;
@@ -58,8 +65,8 @@ static inline int a_cas(volatile int *p, int t, int s)
#define a_barrier a_barrier
static inline void a_barrier()
- __asm__ __volatile__("bl __a_barrier"
- : : : "memory", "cc", "ip", "lr" );
+ register uintptr_t ip __asm__("ip") = __a_barrier_ptr;
+ __asm__ __volatile__( BLX " ip" : "+r"(ip) : : "memory", "cc", "lr" );