mips: add mips-sf subarch support (soft-float)

Userspace emulated floating-point (gcc -msoft-float) is not compatible
with the default mips abi (assumes an FPU or in kernel emulation of it).
Soft vs hard float abi should not be mixed, __mips_soft_float is checked
in musl's configure script and there is no runtime check. The -sf subarch
does not save/restore floating-point registers in setjmp/longjmp and only
provides dummy fenv implementation.

8 files changed, 69 insertions, 3 deletions

diff --git a/arch/mips/bits/fenv.h b/arch/mips/bits/fenv.h
index b2a6db9a..589e71c1 100644
--- a/arch/mips/bits/fenv.h
+++ b/arch/mips/bits/fenv.h
@@ -1,3 +1,7 @@
+#ifdef __mips_soft_float
+#define FE_ALL_EXCEPT 0
+#define FE_TONEAREST  0
+#else
 #define FE_INEXACT    4
 #define FE_UNDERFLOW  8
 #define FE_OVERFLOW   16
@@ -10,6 +14,7 @@
 #define FE_TOWARDZERO 1
 #define FE_UPWARD     2
 #define FE_DOWNWARD   3
+#endif
 
 typedef unsigned short fexcept_t;
 
diff --git a/arch/mips/reloc.h b/arch/mips/reloc.h
index 07fa10a7..4ca81257 100644
--- a/arch/mips/reloc.h
+++ b/arch/mips/reloc.h
@@ -8,7 +8,13 @@
 #define ENDIAN_SUFFIX ""
 #endif
 
-#define LDSO_ARCH "mips" ENDIAN_SUFFIX
+#ifdef __mips_soft_float
+#define FP_SUFFIX "-sf"
+#else
+#define FP_SUFFIX ""
+#endif
+
+#define LDSO_ARCH "mips" ENDIAN_SUFFIX FP_SUFFIX
 
 #define IS_COPY(x) ((x)==R_MIPS_COPY)
 #define IS_PLT(x) 1
diff --git a/configure b/configure
index e4a54181..c622366a 100755
--- a/configure
+++ b/configure
@@ -413,8 +413,10 @@ trycppif __ARMEB__ "$t" && SUBARCH=${SUBARCH}eb
 trycppif __ARM_PCS_VFP "$t" && SUBARCH=${SUBARCH}hf
 fi
 
-test "$ARCH" = "mips" && trycppif "_MIPSEL || __MIPSEL || __MIPSEL__" "$t" \
-&& SUBARCH=${SUBARCH}el
+if test "$ARCH" = "mips" ; then
+trycppif "_MIPSEL || __MIPSEL || __MIPSEL__" "$t" && SUBARCH=${SUBARCH}el
+trycppif __mips_soft_float "$t" && SUBARCH=${SUBARCH}-sf
+fi
 
 test "$ARCH" = "microblaze" && trycppif __MICROBLAZEEL__ "$t" \
 && SUBARCH=${SUBARCH}el
diff --git a/src/fenv/mips-sf/fenv.sub b/src/fenv/mips-sf/fenv.sub
new file mode 100644
index 00000000..9cafca5e
--- /dev/null
+++ b/src/fenv/mips-sf/fenv.sub
@@ -0,0 +1 @@
+../fenv.c
diff --git a/src/setjmp/mips-sf/longjmp.s b/src/setjmp/mips-sf/longjmp.s
new file mode 100644
index 00000000..8e769675
--- /dev/null
+++ b/src/setjmp/mips-sf/longjmp.s
@@ -0,0 +1,25 @@
+.set noreorder
+
+.global _longjmp
+.global longjmp
+.type   _longjmp,@function
+.type   longjmp,@function
+_longjmp:
+longjmp:
+	move    $2, $5
+	bne     $2, $0, 1f
+	nop
+	addu    $2, $2, 1
+1:	lw      $ra,  0($4)
+	lw      $sp,  4($4)
+	lw      $16,  8($4)
+	lw      $17, 12($4)
+	lw      $18, 16($4)
+	lw      $19, 20($4)
+	lw      $20, 24($4)
+	lw      $21, 28($4)
+	lw      $22, 32($4)
+	lw      $23, 36($4)
+	lw      $30, 40($4)
+	jr      $ra
+	lw      $28, 44($4)
diff --git a/src/setjmp/mips-sf/longjmp.sub b/src/setjmp/mips-sf/longjmp.sub
new file mode 100644
index 00000000..e80331b6
--- /dev/null
+++ b/src/setjmp/mips-sf/longjmp.sub
@@ -0,0 +1 @@
+longjmp.s
diff --git a/src/setjmp/mips-sf/setjmp.s b/src/setjmp/mips-sf/setjmp.s
new file mode 100644
index 00000000..38ed5e00
--- /dev/null
+++ b/src/setjmp/mips-sf/setjmp.s
@@ -0,0 +1,25 @@
+.set noreorder
+
+.global __setjmp
+.global _setjmp
+.global setjmp
+.type   __setjmp,@function
+.type   _setjmp,@function
+.type   setjmp,@function
+__setjmp:
+_setjmp:
+setjmp:
+	sw      $ra,  0($4)
+	sw      $sp,  4($4)
+	sw      $16,  8($4)
+	sw      $17, 12($4)
+	sw      $18, 16($4)
+	sw      $19, 20($4)
+	sw      $20, 24($4)
+	sw      $21, 28($4)
+	sw      $22, 32($4)
+	sw      $23, 36($4)
+	sw      $30, 40($4)
+	sw      $28, 44($4)
+	jr      $ra
+	li      $2, 0
diff --git a/src/setjmp/mips-sf/setjmp.sub b/src/setjmp/mips-sf/setjmp.sub
new file mode 100644
index 00000000..b7ad2210
--- /dev/null
+++ b/src/setjmp/mips-sf/setjmp.sub
@@ -0,0 +1 @@
+setjmp.s