From 83350eb17b9cb355e3f08b0340c4f1e8c437fac9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lu=C3=ADs=20Marques?= Date: Wed, 15 Jan 2020 13:24:41 +0000 Subject: fix riscv64 a_cas inline asm operand sign extension This patch adds an explicit cast to the int arguments passed to the inline asm used in the RISC-V's implementation of `a_cas`, to ensure that they are properly sign extended to 64 bits. They aren't automatically sign extended by Clang, and GCC technically also doesn't guarantee that they will be sign extended. --- arch/riscv64/atomic_arch.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/riscv64') diff --git a/arch/riscv64/atomic_arch.h b/arch/riscv64/atomic_arch.h index 41ad4d04..0c382588 100644 --- a/arch/riscv64/atomic_arch.h +++ b/arch/riscv64/atomic_arch.h @@ -15,7 +15,7 @@ static inline int a_cas(volatile int *p, int t, int s) " bnez %1, 1b\n" "1:" : "=&r"(old), "=&r"(tmp) - : "r"(p), "r"(t), "r"(s) + : "r"(p), "r"((long)t), "r"((long)s) : "memory"); return old; } -- cgit v1.2.1