From 200d15479c0bc48471ee7b8e538ce33af990f82e Mon Sep 17 00:00:00 2001 From: Stefan Kristiansson Date: Thu, 17 Jul 2014 22:09:10 +0300 Subject: add or1k (OpenRISC 1000) architecture port With the exception of a fenv implementation, the port is fully featured. The port has been tested in or1ksim, the golden reference functional simulator for OpenRISC 1000. It passes all libc-test tests (except the math tests that requires a fenv implementation). The port assumes an or1k implementation that has support for atomic instructions (l.lwa/l.swa). Although it passes all the libc-test tests, the port is still in an experimental state, and has yet experienced very little 'real-world' use. --- arch/or1k/crt_arch.h | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 arch/or1k/crt_arch.h (limited to 'arch/or1k/crt_arch.h') diff --git a/arch/or1k/crt_arch.h b/arch/or1k/crt_arch.h new file mode 100644 index 00000000..0f381d2d --- /dev/null +++ b/arch/or1k/crt_arch.h @@ -0,0 +1,11 @@ +__asm__("\ +.global _start \n\ +.align 4 \n\ +_start: \n\ + l.ori r3, r1, 0 \n\ + l.addi r2, r0, -8 \n\ + l.and r1, r1, r2 \n\ + l.addi r1, r1, -8 \n\ + l.jal __cstart \n\ + l.ori r2, r0, 0 \n\ +"); -- cgit v1.2.1