From 200d15479c0bc48471ee7b8e538ce33af990f82e Mon Sep 17 00:00:00 2001 From: Stefan Kristiansson Date: Thu, 17 Jul 2014 22:09:10 +0300 Subject: add or1k (OpenRISC 1000) architecture port With the exception of a fenv implementation, the port is fully featured. The port has been tested in or1ksim, the golden reference functional simulator for OpenRISC 1000. It passes all libc-test tests (except the math tests that requires a fenv implementation). The port assumes an or1k implementation that has support for atomic instructions (l.lwa/l.swa). Although it passes all the libc-test tests, the port is still in an experimental state, and has yet experienced very little 'real-world' use. --- arch/or1k/bits/msg.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 arch/or1k/bits/msg.h (limited to 'arch/or1k/bits/msg.h') diff --git a/arch/or1k/bits/msg.h b/arch/or1k/bits/msg.h new file mode 100644 index 00000000..bc8436c4 --- /dev/null +++ b/arch/or1k/bits/msg.h @@ -0,0 +1,15 @@ +struct msqid_ds { + struct ipc_perm msg_perm; + time_t msg_stime; + int __unused1; + time_t msg_rtime; + int __unused2; + time_t msg_ctime; + int __unused3; + unsigned long msg_cbytes; + msgqnum_t msg_qnum; + msglen_t msg_qbytes; + pid_t msg_lspid; + pid_t msg_lrpid; + unsigned long __unused[2]; +}; -- cgit v1.2.1