path: root/src/setjmp/or1k/setjmp.s
diff options
authorStefan Kristiansson <>2014-07-17 22:09:10 +0300
committerRich Felker <>2014-07-18 14:10:23 -0400
commit200d15479c0bc48471ee7b8e538ce33af990f82e (patch)
tree864cc38895b9277384ed3a956f4ad324de2c4455 /src/setjmp/or1k/setjmp.s
parent7bece9c2095ee81f14b1088f6b0ba2f37fecb283 (diff)
add or1k (OpenRISC 1000) architecture port
With the exception of a fenv implementation, the port is fully featured. The port has been tested in or1ksim, the golden reference functional simulator for OpenRISC 1000. It passes all libc-test tests (except the math tests that requires a fenv implementation). The port assumes an or1k implementation that has support for atomic instructions (l.lwa/l.swa). Although it passes all the libc-test tests, the port is still in an experimental state, and has yet experienced very little 'real-world' use.
Diffstat (limited to 'src/setjmp/or1k/setjmp.s')
1 files changed, 24 insertions, 0 deletions
diff --git a/src/setjmp/or1k/setjmp.s b/src/setjmp/or1k/setjmp.s
new file mode 100644
index 00000000..8de4d3c2
--- /dev/null
+++ b/src/setjmp/or1k/setjmp.s
@@ -0,0 +1,24 @@ __setjmp _setjmp setjmp
+.type __setjmp,@function
+.type _setjmp,@function
+.type setjmp,@function
+ l.sw 0(r3), r1
+ l.sw 4(r3), r2
+ l.sw 8(r3), r9
+ l.sw 12(r3), r10
+ l.sw 16(r3), r14
+ l.sw 20(r3), r16
+ l.sw 24(r3), r18
+ l.sw 28(r3), r20
+ l.sw 32(r3), r22
+ l.sw 36(r3), r24
+ l.sw 40(r3), r26
+ l.sw 44(r3), r28
+ l.sw 48(r3), r30
+ l.jr r9
+ l.ori r11,r0,0