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| author | Rich Felker <dalias@aerifal.cx> | 2014-07-19 15:51:12 -0400 |
|---|---|---|
| committer | Rich Felker <dalias@aerifal.cx> | 2014-07-19 15:51:12 -0400 |
| commit | bcad48439494820989f5867c3f8ccfa6aae2909f (patch) | |
| tree | 96b9f234bd245c189e8a7a1cef9545efb8fe6b58 /src/complex/casinhf.c | |
| parent | a294f539c78c6ba0a2786ef3c5b2a1210a33864e (diff) | |
| download | musl-bcad48439494820989f5867c3f8ccfa6aae2909f.tar.gz | |
fix missing barrier instructions in mips atomic asm
previously I had wrongly assumed the ll/sc instructions also provided
memory synchronization; apparently they do not. this commit adds sync
instructions before and after each atomic operation and changes the
atomic store to simply use sync before and after a plain store, rather
than a useless compare-and-swap.
Diffstat (limited to 'src/complex/casinhf.c')
0 files changed, 0 insertions, 0 deletions