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authorRich Felker <dalias@aerifal.cx>2012-10-15 18:51:53 -0400
committerRich Felker <dalias@aerifal.cx>2012-10-15 18:51:53 -0400
commit9ec4283b28cf676292fd5c6f681bef1e90e30c18 (patch)
tree2897be56744c39158a3e53adfc4e3569b3f8547d /arch
parentd5304147b983f309ed0c9050e3b8b6f2c9f87f43 (diff)
downloadmusl-9ec4283b28cf676292fd5c6f681bef1e90e30c18.tar.gz
add support for TLS variant I, presently needed for arm and mips
despite documentation that makes it sound a lot different, the only ABI-constraint difference between TLS variants II and I seems to be that variant II stores the initial TLS segment immediately below the thread pointer (i.e. the thread pointer points to the end of it) and variant I stores the initial TLS segment above the thread pointer, requiring the thread descriptor to be stored below. the actual value stored in the thread pointer register also tends to have per-arch random offsets applied to it for silly micro-optimization purposes. with these changes applied, TLS should be basically working on all supported archs except microblaze. I'm still working on getting the necessary information and a working toolchain that can build TLS binaries for microblaze, but in theory, static-linked programs with TLS and dynamic-linked programs where only the main executable uses TLS should already work on microblaze. alignment constraints have not yet been heavily tested, so it's possible that this code does not always align TLS segments correctly on archs that need TLS variant I.
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/pthread_arch.h9
-rw-r--r--arch/arm/reloc.h4
-rw-r--r--arch/i386/pthread_arch.h3
-rw-r--r--arch/microblaze/pthread_arch.h2
-rw-r--r--arch/mips/pthread_arch.h12
-rw-r--r--arch/mips/reloc.h11
-rw-r--r--arch/x86_64/pthread_arch.h3
7 files changed, 33 insertions, 11 deletions
diff --git a/arch/arm/pthread_arch.h b/arch/arm/pthread_arch.h
index 5f96f2b0..43a1c012 100644
--- a/arch/arm/pthread_arch.h
+++ b/arch/arm/pthread_arch.h
@@ -1,6 +1,9 @@
-typedef pthread_t (*__pthread_self_func_t)(void) __attribute__((const));
+typedef char *(*__ptr_func_t)(void) __attribute__((const));
-#define __pthread_self ((__pthread_self_func_t)0xffff0fe0)
+#define __pthread_self() \
+ ((pthread_t)(((__ptr_func_t)0xffff0fe0)()+8-sizeof(struct pthread)))
+
+#define TLS_ABOVE_TP
+#define TP_ADJ(p) ((char *)(p) + sizeof(struct pthread) - 8)
-#define CANCEL_REG_SP 16
#define CANCEL_REG_IP 18
diff --git a/arch/arm/reloc.h b/arch/arm/reloc.h
index c37af07b..b41314de 100644
--- a/arch/arm/reloc.h
+++ b/arch/arm/reloc.h
@@ -34,8 +34,8 @@ static inline void do_single_reloc(
break;
case R_ARM_TLS_TPOFF32:
*reloc_addr += def.sym
- ? def.sym->st_value - def.dso->tls_offset
- : 0 - self->tls_offset;
+ ? def.sym->st_value + def.dso->tls_offset + 8
+ : self->tls_offset + 8;
break;
}
}
diff --git a/arch/i386/pthread_arch.h b/arch/i386/pthread_arch.h
index 0ea0aaca..1c06c764 100644
--- a/arch/i386/pthread_arch.h
+++ b/arch/i386/pthread_arch.h
@@ -5,5 +5,6 @@ static inline struct pthread *__pthread_self()
return self;
}
-#define CANCEL_REG_SP 7
+#define TP_ADJ(p) (p)
+
#define CANCEL_REG_IP 14
diff --git a/arch/microblaze/pthread_arch.h b/arch/microblaze/pthread_arch.h
index 6c0ab5ad..259d3d61 100644
--- a/arch/microblaze/pthread_arch.h
+++ b/arch/microblaze/pthread_arch.h
@@ -5,4 +5,6 @@ static inline struct pthread *__pthread_self()
return self;
}
+#define TP_ADJ(p) (p)
+
#define CANCEL_REG_IP 32
diff --git a/arch/mips/pthread_arch.h b/arch/mips/pthread_arch.h
index 77b7330d..f8e35ae4 100644
--- a/arch/mips/pthread_arch.h
+++ b/arch/mips/pthread_arch.h
@@ -1,12 +1,16 @@
static inline struct pthread *__pthread_self()
{
- struct pthread *self;
#ifdef __clang__
- __asm__ __volatile__ (".word 0x7c03e83b ; move %0, $3" : "=r" (self) : : "$3" );
+ char *tp;
+ __asm__ __volatile__ (".word 0x7c03e83b ; move %0, $3" : "=r" (tp) : : "$3" );
#else
- __asm__ __volatile__ (".word 0x7c03e83b" : "=v" (self) );
+ register char *tp __asm__("$3");
+ __asm__ __volatile__ (".word 0x7c03e83b" : "=r" (tp) );
#endif
- return self;
+ return (pthread_t)(tp - 0x7000 - sizeof(struct pthread));
}
+#define TLS_ABOVE_TP
+#define TP_ADJ(p) ((char *)(p) + sizeof(struct pthread) + 0x7000)
+
#define CANCEL_REG_IP (3-(union {int __i; char __b;}){1}.__b)
diff --git a/arch/mips/reloc.h b/arch/mips/reloc.h
index 785489ed..f5e9c77b 100644
--- a/arch/mips/reloc.h
+++ b/arch/mips/reloc.h
@@ -23,6 +23,17 @@ static inline void do_single_reloc(
case R_MIPS_COPY:
memcpy(reloc_addr, (void *)sym_val, sym_size);
break;
+ case R_MIPS_TLS_DTPMOD32:
+ *reloc_addr = def.dso ? def.dso->tls_id : self->tls_id;
+ break;
+ case R_MIPS_TLS_DTPREL32:
+ *reloc_addr += def.sym->st_value;
+ break;
+ case R_MIPS_TLS_TPREL32:
+ *reloc_addr += def.sym
+ ? def.sym->st_value + def.dso->tls_offset - 0x7000
+ : self->tls_offset - 0x7000;
+ break;
}
}
diff --git a/arch/x86_64/pthread_arch.h b/arch/x86_64/pthread_arch.h
index 836187f5..77c8387c 100644
--- a/arch/x86_64/pthread_arch.h
+++ b/arch/x86_64/pthread_arch.h
@@ -5,5 +5,6 @@ static inline struct pthread *__pthread_self()
return self;
}
-#define CANCEL_REG_SP 15
+#define TP_ADJ(p) (p)
+
#define CANCEL_REG_IP 16